Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization

ABSTRACT

A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS&#39;89 is used as a testing circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to optimization of the skew of a digital synchronous VLSI system and particularly to the acceleration of operation speed and the reduction of complexity.

2. Description of Related Art

Along with nano-technology that prevails, what is concerned in a high-performance integrated circuit design includes higher design complexity, high-speed clock frequency, lower interconnect width, and lower Supply Voltage, which increases the difficulty of high-performance integrated circuit design. Besides speed and surface area, reliability must be considered for the critical target of optimization.

A high-frequency digital synchronous VLSI circuit operates with a region assembly logic circuit, in this way, registers must be arranged in a specified region of the circuit and are controlled by clock signals; if the digital synchronous circuit is made to operate normally, the clock signals must be transmitted to each of the registers at different time of intervals, and thus the transmission of clock signals is implemented with the aspects of circuit and interconnect.

When a high-speed synchronous circuit gradually raise a clock frequency, the transmission of a clock signal in a Clock Distribution Network is a key point, which may raise clocks of a circuit and may be a feature required by the circuit for normal operation. How to effectively use clock variance for minimization of a clock cycle is a topic for discussion of clock variance scheduling and optimization. The time for the clock signal to reach a register must be corresponding to the limits of zero clocking and double clocking, and thus the circuit may work normally. The time for the clock signal to reach each register is not necessarily synchronous. Thus, effectively using the clock variance may not only make the circuit constantly operate normally but also raise the performance of circuit. Therefore, besides a conventional algorithm of clock variance scheduling and optimization, a conventional algorithm of polynomial time complexity is proposed. Due to the limit of clock cycle, results of multiple clock variation scheduling are given. In this invention, besides the optimization of clock variation scheduling, operation time is also taken seriously so that this invention is practicable.

SUMMARY OF THE INVENTION

In this invention, a quadratic equation cost function is mainly used to analyze an ideal value of skew and an error between feasible solutions. The depth first search algorithm, the minimum spanning tree, the concept of sparse matrix multiplication, and the Conjugate Gradients algorithm are used to speed up the operation and lower the complexity. Next, an ISCAS'89 is used as a testing circuit for outputting a simulation result. The methods proposed in this invention may make all the skews in the circuit reach to a target value. When circuit clocks may provide the circuit with correct running time, the reliability and performance of circuit increase.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart of a synchronous system;

FIG. 2 is a flow chart of a local data path;

FIG. 3 is a flow chart of the grogram according to this invention;

FIG. 4A is a digital synchronous circuit diagram;

FIG. 4B is a simplified digital synchronous circuit diagram;

FIG. 4C is a view of a result given from the modeling of circuit;

FIG. 5 shows a circuit diagram illustrating the clock skew;

FIG. 6 is a flow chart of implementation of the Interior-point algorithm;

FIG. 7A is a exemplary view of a spanning tree for a circuit;

FIG. 7B is a view of a spanning tree;

FIG. 7C is a view of a first loop of the spanning tree;

FIG. 7D is a view of a second loop of the spanning tree;

FIG. 7E is a view of a third loop of the spanning tree;

FIG. 7F is a view of a fourth loop of the spanning tree;

FIG. 8A is a view of a zero skew caused from the execution of a circuit S838.1;

FIG. 8B is a view of a non-zero skew caused from the execution of the circuit S838.1;

FIG. 9A is a view of a zero skew caused from the execution of a circuit S5378;

FIG. 9B is a view of a non-zero skew caused from the execution of the circuit S5378;

FIG. 10 gives a dummy program in a spanning tree algorithm; and

FIG. 11 gives a dummy program in a conjugate gradient method.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, the present invention will be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.

Generally speaking, a digital synchronous VLSI system proposed in a conventional technology comprises three elements:

-   -   1. combinational logic circuit, a primary circuit for a system         to execute the operation, comprising several logic gates;     -   2. clock-based storage element that is made up with registers to         store results given from the operation by the logic circuit;     -   3. Clock Distribution Network providing the input of clock-based         storage element, which coordinates the synchronization of system         by means of the control of time difference, the synchronous         system being shown in FIG. 1.

Clock Skew and Security Range

The combinational logic between the two registers adjacent in proper sequence to each other is called a local data path. FIG. 2 is a schematic view illustrating a local data path from a register R_(i) to a register R_(f), in which C_(i) and C_(f) represent clock input time of R_(i) and R_(f), respectively, and D_(Pmin) ^(i,f) and P_(Pmax) ^(i,f) indicate the minimum path delay and maximum path delay of the data path, respectively.

The risk of clock is caused by double clocking and zero clocking. The so-called skew means a value of difference of a clock input R_(i) from that R_(i) between the two registers R_(i) and R_(i) adjacent to each other,

T _(Skew)(i,f)=C _(i) −C _(f)   (1)

where the shift may cause the circuit to wrongly operate.

Double Clocking

Double clocking indicates that a data signal is triggered two times before a clock signal from a register is not registered. Thus, a first triggered data signal is neglected because of departure from hold time.

As shown in FIG. 2, when the data of a register R_(i) is transmitted from an output terminal Q_(i) in period k of clock signal C_(i), and after the operation of combinational logic circuit, the data must be received from an input terminal D_(f) of the register R_(f) in period k+1 of clock signal C_(f) for proper operation. However, if the signal received from the input terminal R_(f) of register R_(f) comes too early, the signal will be received from the input terminal R_(f) of register R_(f) in period k of clock signal R_(f), and thus this signal covers the former signal, thereby making the circuit operate wrongly. Thus, a time limit must be applied to the signal received from the input terminal R_(f) of register R_(f) for the proper operation of the circuit:

t _(Am) ^(Ff)≧(C _(f) +kT _(Cp)+_(L) ^(F))+δ_(H) ^(Ff)   (2)

where t_(Am) ^(Ff) is the minimum time for the signal to reach the input terminal D_(f) of register R_(f), T_(CP) is a period of clock signal, Δ_(L) ^(F) is a tolerant error of the clock signal, and δ_(H) ^(Ff) is the hold time of register R_(f).

t_(Am) ^(Ff) is made up with two sets of time that may be divided, the output time of a former register R_(i) and the transfer time of combinational logic circuit:

t _(Am) ^(Ff) =t _(Qm) ^(Fi) +D _(Pm) ^(i,f)   (3)

where t_(Qm) ^(Fi)=C_(i)+kT_(CP)−Δ_(L) ^(F)+D_(CQm) ^(F) gives the time of output terminal Q_(i) of the data register R_(i), and D_(Pm) ^(i,f) is a minimum value of the transfer time of combinational logic circuit between the registers R_(i) and R_(f). Thus, equation (2) may be changed into:

(C+kT _(CP)−Δ_(L) ^(F) +D _(CQm) ^(Ff))+D _(Pm) ^(i,f)≧(C _(f) +kT _(CP) +Δ _(L) ^(F))+δ_(H) ^(Ff)   (4)

After it is simplified, an equation is given below:

T _(Skew)(i,f)≧−(D_(Pm) ^(i,f) +D _(CQm) ^(Fi))+δ_(H) ^(Ff)+2Δ_(L) ^(F)   (5).

Equation (5) is given from double clocking, and thus it is deduced that the minimum limit must be applied to the skew between the registers R_(i) and R_(i). From the above description, no clock period is given in equation (5), so equation (5) is not related to the clock period. Therefore, when the double clocking is caused in the circuit, raising the clock period is not helpful. It is apparent that the double clocking is more dangerous; namely, the clock risk in the circuit is almost caused by the departure from hold time.

Zero Clocking

Zero clocking indicates that a clock signal has been triggered before a data signal does not reach a register; thus, the register transmits an erroneous value mainly due to the departure from built-up time.

As shown in FIG. 2, if the signal received from the input terminal R_(f) of register R_(f) comes too late, the signal will not be received from the input terminal R_(f) of register R_(f) in period k+1 of clock signal R_(f), and no signal is inputted to the register R_(f), likewise making the circuit operate wrongly. Thus, a time limit must be applied to the signal received from the input terminal R_(f) of register R_(f) for the proper operation of the circuit:

t _(AM) ^(Ff)≦(C _(f)+(k+1)T _(CP)−Δ_(L) ^(F))−δ_(S) ^(Ff)   (6)

where t_(AM) ^(Ff) is the maximum time for the signal to reach the input terminal t_(AM) ^(Ff) of register t_(AM) ^(Ff), t_(AM) ^(Ff) is a period of clock signal, t_(AM) ^(Ff) is a tolerant error of the clock signal, and t_(AM) ^(Ff) is the built-up time of register t_(AM) ^(Ff).

t_(AM) ^(Ff) may be made up with two sets of time:

t _(AM) ^(Ff) =t _(QM) ^(fi) +D _(PM) ^(i,f)   (7)

where t_(QM) ^(Fi)=C_(i)+kT_(CP)+Δ_(L) ^(F)+D_(CQM) ^(Fi) gives the time of output terminal t_(QM) ^(Fi)=C_(i)+kT_(CP)+Δ_(L) ^(F)+D_(CQM) ^(Fi) of the data register t_(QM) ^(Fi)=C_(i)+kT_(CP)+Δ_(L) ^(F)+D_(CQM) ^(Fi), and t_(QM) ^(Fi)=C_(i)+kT_(CP)+Δ_(L) ^(F)+D_(CQM) ^(Fi) is a maximum value of the transfer time of combinational logic circuit between the registers t_(QM) ^(Fi)=C_(i)+kT_(CP)+Δ_(L) ^(F)+D_(CQM) ^(Fi) and t_(QM) ^(Fi)=C_(i)+kT_(CP)+Δ_(L) ^(F)+D_(CQM) ^(Fi). Thus, equation (6) may be changed into:

(t _(QM) ^(Fi) =C _(i) +kT _(CP) +Δ _(L) ^(F) +D _(CQM) ^(Fi))+D _(PM) ^(i,f)≦(C _(f)+(k+1)T _(CP)−Δ_(L) ^(F))−δ_(S) ^(Ff)   (8)

After it is simplified, an equation is given below:

T _(Skew)(i,f)≦T _(CP)−(D _(PM) ^(i,f) +D _(CQM) ^(Fi)+δ_(S) ^(Ff))−2Δ_(L) ^(F)   (9)

Equation (9) is given from zero clocking, and thus it is deduced that the maximum limit must be applied to the skew between the registers R_(i) and R_(i). From equation (9), two critical results may be known:

-   -   1. The clock period may be adjusted to avoid the clock risk         caused by zero clocking; thus, proper exaltation of the clock         period may increase an upper limit of the skew, the flexibility         of skew.     -   2. The clock period T_(CP) is not necessarily higher than         (D_(PM) ^(i,f)+D_(CQM) ^(Fi)+δ_(S) ^(Ff)) because a value given         from the clock shift may be positive and also negative, and         thus, in equation (9), at this time of T_(CP)−(D_(PM)         ^(i,f)+D_(CQM) ^(Fi)+δ_(S) ^(Ff))<0, only under the condition of         clock shift T_(Skew)(i,f)<0, zero clocking will not be caused in         the local path.

In the design of synchronous circuit, it is assumed that all the registers are triggered at the same time; namely, it is a so-called target to zero skew. In fact, the time for the clock signal to reach the register must be corresponding to the limits of zero clocking and double clocking, and thus the circuit may work normally. Thus, the skew must be in a permissible range and thus the local data path may work safely.

Scheduling and Optimization of the Clock Skew

After the safe range of skew in the local data path is defined, the skew scheduling and optimization is implemented. As shown in FIG. 3 illustrating a flow chart of execution of a program according to this invention,

at step 1 of reading a test circuit 101, a circuit to be tested is first read in the program;

at step 2 of building up a circuit model 102, before optimization, pre-processing of and correlation analysis on the circuit, including establishment of the circuit model and linear-related analysis on the model must be carried out through step 102;

at step 3 of building up a minimum spanning tree 103, a minimum spanning tree is built up;

at step 4 of building up a matrix M=B×B^(l) 104, a matrix M=B×B^(l) is built up;

at step 5 of calculating a Lagrange multiplier 105, a Conjugate Gradients algorithm is used to calculate a Lagrange multiplier;

at step 6 of calculation for a feasible solution to skew, calculation is done for a feasible solution to skew;

at step 7 of checking the conformity with condition 107, the condition is checked for the conformity with condition Bs=0, l<s<u;

at step of fine tuning a value of <ideal skew> 108, if the condition does not meet the condition set at step 7, a value of <ideal skew> fine tuned, and step 5 returns;

at step of outputting a result 109, if the condition meets the condition set at step 7, a result is outputted.

Construction of a Circuit Model

A digital VLSI circuit comprises many combinational logic circuits and registers, and a simple digital synchronous circuit, as shown in FIG. 4A, comprises four registers R1, R2, R3, and R4 and four logic gates G1, G2, G3, and G4. The skew between registers is a main issue, and thus after the circuit is simplified, only types of registers connecting with each other remains, as shown in FIG. 4B, in a graphics theory based on a conventional technology. Next, the registers are disconnected for prevention of the skew. Finally, [l_(i), u_(i)] is used as a value in a safe range of each period of skew and [l_(i),u_(i)] is used as a mark of each period of link. s^(i) comprises a skew value and link-up direction of the data path, as shown in FIG. 4C.

There is almost only a path (local data path) between registers adjacent to each other, but there might be more than two connections of registers adjacent to each other. At this time, another processing manner is divided into two conditions: a first condition when the direction of connections are the same, maximum and minimum values in the safe range of skew of each connection must intersect: ∩└l_(z(i)), u_(z(i))┘; a second condition when the direction of connections are opposite, a direction must be set to a last direction, and when the direction of connections is different from that specified, the maximum and minimum values in the safe range of skew are exchanged and marked with a negative sign and finally intersect the safe range of skew in each period of connection: ∩└l_(z(i)), u_(z(i))┘.

Linear Dependence of the Clock Skew

Generally, a large circuit comprises very many feedback feedforeward data paths. As shown in FIG. 5, the sets of skew s₄ and s₄ are equal, s₄=s₄, because of the path from a register s₄ finally to a register s₄. The correlated data paths may form a loop, and in FIG. 5, two loops are provided as shown below:

C₁=R₁, s₁, R₃, s₄, R₂, s₃, R₁

C₂=R₂, s₄, R₃, s₂, R₄, R₅, R₂

and thus equation (10) is given below:

s ₁ −s ₃ +s _(s)=0

s ₂ −s ₄ +s ₅=0   (10)

and next, equation (10) is expressed in the form of matrix:

$\begin{matrix} {{{Bs} = 0}{{where}\mspace{14mu} B} = {\quad{\begin{bmatrix} 1 & 0 & {- 1} & 1 & 0 \\ 0 & 1 & 0 & {- 1} & 1 \end{bmatrix} = {{\left\lbrack {I\mspace{14mu} C} \right\rbrack \mspace{14mu} \backprime \mspace{14mu} I} = {{\begin{bmatrix} 1 & 0 \\ 0 & 1 \end{bmatrix}\mspace{14mu} \backprime \mspace{14mu} C} = {\begin{bmatrix} {- 1} & 1 & 0 \\ 0 & {- 1} & 1 \end{bmatrix}.}}}}}} & (11) \end{matrix}$

Optimization of the Clock Skew

In this invention, there are two methods of optimization of the skew, a least-square error method and an interior-point method, being described below.

1. Least-Square Error Method

It is assumed that a circuit model has been built up, comprising r register(s) and p local data path(s), in which p>r, so there is/are p skew value(s) S=[s₁s₂. . . s_(p)]^(t) to be calculated. The number of register(s) is r, so only r−1 local data path is required to connect to all the registers, in which the r−1 local data path is called main skew and the other one (p−r+1) is called chord skew. Thus, S may be changed into S=[^(S S)], in which S=[s₁ s₂. . . s_(p−r+1)]^(t) is chord skew and s^(b)=[S_(p−r+2). . . S_(p)]^(t) is main skew. Each skew s_(i) is corresponding to its safe range s_(i) and an intermediate value in the safe range stands for ideal skew. Thus, a set of ideal p clock shift value g=[g₁ g₂ . . . g_(p)]^(t) is likewise given that is equal to s=[s^(c) s^(b)], in which g may also be reduced to g=[g^(c) g^(b)]. For the purpose, it is expected that the practical clock shift s=[s₁ s₂. . . s_(p)]^(t) is close to the ideal clock shift value g=[g₁ g₂ . . . g_(p).]^(t) as possible as it can. Thus, this issue is put into formula for the least-square error method:

$\begin{matrix} \min^{ɛ = {\sum\limits_{k = 1}^{p}\; {({s_{k} - g_{k}})}^{2}}} & (12) \end{matrix}$

where upper and lower limits are applied to each clock shift S and the clock shift S must meet the linear dependence proposed for the clock shift; thus, a limited condition of equation (12) is:

Bs=0

l≦s≦u

equation (12) is expressed in the form of matrix:

ε=(s−g)²=(s)²−2g's+(g)² =s ^(l) s−2g ^(t) s+g ^(t) g

where g^(t)g is a constant and {tilde over (ε)}−2 g^(t)s; thus, equation (12) is changed into:

min {tilde over (ε)}=s^(t) s−2g ^(t) s   (13)

condition limit: Bs=0 where the limited condition l≦s≦u is temporarily neglected, and the upper and lower limits are not checked until the clock shift s is fully calculated.

Next, a method of quadratic equation of a conventional technology is used to calculate for a feasible solution to clock shift s=[s^(c) s^(b)]. At first, the Lagrange multiplier is introduced to equation (13) for a Lagrangean function (s, λ):

(s, λ)={tilde over (ε)}+λ′Bs=s ^(t) s−2g ^(t) s+λ′Bs   (14)

{tilde over (ε)} is a fixed point in the Lagrangean function Δ(s,λ)=0, so 0 is given from a first-order partial differentiation, namely Δ_(s)(s,λ)=0 ∇_(λ)(s, λ)=0_(s).

From the above description,

${\nabla_{\lambda}\left( {s,\lambda} \right)} = {{\nabla_{\lambda}\left( {{s^{t}s} - {2g^{t}s} + {\lambda^{t}{Bs}}} \right)} = {\left. {Bs}\Rightarrow \right.\begin{matrix} {{{2s} + {B^{t}\lambda}} = {2g}} \\ {{Bs} = 0} \end{matrix}}}$

expressed in the form of matrix:

$\begin{matrix} {{\begin{bmatrix} {2I_{p}} & B^{t} \\ B & 0 \end{bmatrix}\begin{bmatrix} s \\ \lambda \end{bmatrix}} = {2\begin{bmatrix} g \\ 0 \end{bmatrix}}} & (15) \end{matrix}$

From equation (15), a second-row element B is eliminated in the Gaussian elimination method; namely, a first-row element is multiplied by

$\frac{1}{2}B$

and then added to the second-row element for a result given below:

$\begin{matrix} {{\begin{bmatrix} {2I_{p}} & B^{t} \\ 0 & {BB}^{t} \end{bmatrix}\begin{bmatrix} s \\ \lambda \end{bmatrix}} = {2\begin{bmatrix} g \\ {Bg} \end{bmatrix}}} & (16) \end{matrix}$

From equation (16), two formulae may be given:

$\begin{matrix} {\lambda = {2M^{- 1}{Bg}}} & \; \\ {s = {{{- \frac{1}{2}}B^{t}\lambda} + g}} & (17) \\ {{{{where}\mspace{14mu} M} = {{BB}^{t} = {{\left\lbrack {I\mspace{14mu} C} \right\rbrack \begin{bmatrix} I \\ C \end{bmatrix}} = {I + {CC}}}}},} & \; \end{matrix}$

and if s and g are expressed as s=[s^(c) s^(b)] and g=[g^(c) g^(b)], then equation (17) may be changed into:

$\begin{matrix} {{\lambda = {2M^{- 1}{Bg}}}{s^{b} = {{{- \frac{1}{2}}C^{t}\lambda} + g^{b}}}{s^{c} = {{{- \frac{1}{2}}\lambda} + g^{c}}}} & (18) \end{matrix}$

The values of vectors B and g in equation (13) are known and M is also a matrix given after being multiplied by B, so the practical clock shift s=[s^(c) s^(b)] in the circuit may be given.

Interior-Point Method as a Second Method

The interior-point method has been used to deal with the issue of optimization in recent years because a feasible solution to this problem in this method depending on quite a little times of iteration, and thus processing time is greatly improved. In this invention, a last experimental data is solved in the least-square error method.

2. Interior-Point Method

Generally speaking, the interior-point method on the basis of a theory comprises three methods: Fiacco and McCormick logarithmical barrier function method that is used for solving the issue of optimization of an inequality condition, Lagrange's method that is used for solving the issue of optimization of an equality condition, and Newton's iteration method that is used for solving the issue of system of non-linear equations without any condition. The following original issue of interior-point method is considered:

$\begin{matrix} {{{\min \frac{1}{2}x^{T}{Qx}} + {c^{T}x}}{{s.t.{Ax}} = b}{\underset{\_}{x} \leq x \leq \overset{\_}{x}}} & (19) \end{matrix}$

A quadratic-expression objective function, a threshold condition, an inequality threshold condition are included.

The logarithmical barrier function method is used mainly because a barrier parameter μ starts from a certain positive value as an initial value and is gradually close to 0. Theoretically, when being reduced to 0, the barrier parameter tends towards a minimum value of the original issue. The interior-point method comprises the following steps, as shown in FIG. 6.

At step 1 of building up an initial value 201, an initial value is built up, comprising an original variable and an antithetic variable.

At step 2 of calculating a barrier parameter 202, a barrier parameter is calculated, in which if a solution is convergence, the step ends, and if not, step 3 enters.

At step 3 of solving a matrix-vector equation 203, a matrix-vector equation is solved.

At step 4 of solving variates 204, the variates of an original variable and those of an antithetic variable are calculated.

At step 5 of calculating a step size 205, the step sizes of original and antithetic variables are calculated.

At step 6 of updating variables 206, all the original and antithetic variables are updated.

Employment of an Algorithm

After the issue of clock shift is put into the formula of quadratic equation, with a known value, the practical clock shift s=[s ^(c) s ^(b)] is calculated. Next, programming is performed, in which 4 important steps as follows must be specially researched.

-   -   1. Construction of a circuit model in this invention, the clock         shift value between the registers adjacent to each other in the         digital VLSI circuit is mainly calculated. Thus, the circuit         must be modeled and, as shown in FIG. 4C, a pure register-based         circuit model is formed. In this invention, a Depth First Search         Algorithm is used to form the structure.     -   2. Circuit loop search: in equation (11), from Bs=0, matrix B is         just a loop of a circuit. Thus, the loops in the circuit must be         found, and generally, a null space method may be used to find         all the loops. From a testing result and an analysis, it is         found that much time and many memories are required in this null         space method, and thus it is replaced with Fundamental Loop and         the concept of spanning tree is implemented.     -   3. Matrix multiplication: after the circuit loop search ends,         the matrix B is given. Next, matrix multiplication is required         for the matrix M=BB′ in equation (17), so the concept of sparse         matrix multiplication is used to save much time in operation.     -   4. Solution to the Ax=b issue: likewise, in equation (17), the         Lagrange multiplier λ=2M ⁻¹ B g must be calculated. The type of         equation is like Ax=b as a mathematic issue, being solved in an         inverse matrix method but inefficient. In this invention, the         conjugate gradient algorithm is used, and from a testing result,         it is found that this algorithm is effective and works fast.

Depth First Search Algorithm

When a circuit is read in, the interconnection of circuit must be built up. Thus, a next clock shift calculation may be carried out, so the circuit must be modeled. The clock shift is the difference of clocks between the registers adjacent to each other, so the circuit model must be formed into the register-based model. In this invention, the Depth First Search Algorithm is used to construct the circuit model, and a recursion method is used as a skill, indicating that the program call itself until no node. After the Depth First Search Algorithm is used in this invention to construct the circuit model, except registers, logic gates in the circuit will be recorded in the form of value, and the generated model is the type of registers connected to each other.

Spanning Tree

From the description above, before the clock shift is transformed into the quadratic equation, all the loops in the circuit must be searched, in which the loops are independent. Among the methods of searching all the loops, the null space method is widely used but inefficient. Thus, in this invention, at step 3 in FIG. 3, the spanning tree method is a substitute and works with the Depth First Search method to very efficiently form all the loops in the circuit. The loop sets are matrices B. After the matrix at step 4 shown in FIG. 3 is constructed, the quadratic equation programming may be executed. Steps of forming all the loops in the circuit in the spanning tree are described below.

1. A simple example is given for explanation, as shown in FIG. 7A. This circuit comprises 5 registers and 8 connections (local data paths). First of all, minimum connections that link to all the registers are found. This circuit comprises 5 registers, so 4 connections link to all the registers. At this time, the spanning tree method is used. In this invention, the spanning tree is searched in the Depth First Search algorithm as an example for a next step of explanation.

-   -   2. In the exemplary circuit shown in FIG. 7A, the Depth First         Search algorithm is used to find the spanning tree         R₁→s₅→R₃→s₆→R₂→s₁→R₅→s₈R₄, as shown in FIG. 7B.     -   3. Then, connection s₁ is linked and thus a first loop         C₁=s₁−s₅+s₆ is shown, as illustrated in FIG. 7C.     -   4. Connection s₂ is linked and thus a second loop         C₂=s₁+s₅−s₆−s₇+s₈ is found, as shown in FIG. 7D.     -   5. Connection s₃ is linked and thus a third loop C₃=s₃−s₆+s₇+s₈         is found, as shown in FIG. 7E.     -   6. Connection s₄ is linked and thus a fourth loop C₄=s₄−s₆+s₇ is         found, as shown in FIG. 7F.     -   7. After all the loops are done, a matrix B may be formed:

$B = {\begin{bmatrix} 1 & 0 & 0 & 0 & {- 1} & 1 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & {- 1} & 1 & 1 \\ 0 & 0 & 1 & 0 & 0 & {- 1} & 1 & 1 \\ 0 & 0 & 0 & 1 & 0 & {- 1} & 1 & 0 \end{bmatrix} = \left\lbrack {I\mspace{14mu} C} \right\rbrack}$

Sparse Matrix Multiplication

Matrix multiplication takes very much time and occupies more memory, so the complexity will reach O(n³), if two matrices are just multiplied in no skill, in which n is margin length of matrix; thus, Sparse Matrix Multiplication (proposed in year 1996 by G. H. Golub and C. F. V. Loan, Matrix Computations. Johns Hopkins University Press, Baltimore, proposed in year 2002 by F. Y. Chang, A x=b in C++. sparse matrix technique. NCTU press) is used at the step of this invention for time saving; the step is matrix M=BB′, in which B=[I C], and thus

${M = {{BB}^{t} = {{\left\lbrack {I\mspace{14mu} C} \right\rbrack \begin{bmatrix} I \\ C \end{bmatrix}} = {T + {CC}^{t}}}}};$

the model of unit matrix I is fixed, so only the matrix B is required to be saved and only CC′ is acceptable given from the matrix M.

Although overwhelming majority of operation time and memory occupation is saved, because digital VLSI circuit interconnect is very complicated, the matrix multiplication CC′ must still be improved. It is found in this invention that the matrix CC′ is very sparse because most of the values are 0, and thus if all elements are stored and multiplied, more memory and time will be consumed and wasted. Thus, the concept of sparse matrix multiplication is available in this invention to record non-zero elements in the matrix C, being described as follows:

1. Each non-zero element as a row vector is recorded sequentially.

2. Each non-zero element as a column vector is recorded sequentially.

3. Each non-zero element as a value is recorded sequentially.

Other zero elements are not recorded. As shown in FIG. 7E, non-zero elements in the matrices are indicated with *, and the matrices are multiplied by the non-zero elements; from a result given from the circuit under test, excellent improvement on time saving is made.

Conjugate Gradient Algorithm

After the clock shift is transformed into the quadratic equation, at step 105, in the conjugate gradient algorithm followed by a series of deduction processes and the Lagrange multiplier, equation (17) is given. In equation (17), the form of Lagrange multiplier λ=2 M ⁻¹ B g is like the mathematic issue of Ax=b, in which the matrix M is same as the matrix in Ax=b and the vector B g is same as the vector b in Ax=b. In a current knowledge base, there are many kinds of solutions to the mathematic issue of Ax=b, and the matrix M is used as an inverse matrix, which is immediate but takes much more time. After consideration is taken for all aspects, the conjugate gradient algorithm is used to solve the mathematic issue of Ax=b.

The conjugate gradient algorithm is a renowned algorithm in scientific calculation, and the Krylov subspace iteration algorithm is developed from this algorithm. The conjugate gradient algorithm was proposed by Hestenes & Stiefel in 1952 at the earliest days. CG algorithm is used to solve a symmetrical system in positive definite form quite effectively, and in the method of iteration, several rows of direction vectors are generated to update an iteration solution and an remainder vector. Although the generated arrays becomes larger and larger, only a small number of vectors are stored. Thus, the iteration of the conjugate gradient algorithm is used in this invention to obtain the Lagrange multiplier λ=2 M ⁻¹ B g, in which when a residual error as a condition is small enough to stop the iteration, a set of operation result is generated. In the mathematic issue of Ax=b, the residual error is the sum of errors between a former set of x and a later set of x. Enough small residual error indicates that the value x obtained in the conjugate gradient algorithm almost approaches a correct value x, and thus the iteration stops.

Basically, in the conjugate gradient algorithm, a conjugate direction is applied for the concept of search direction, and a proper value s, called a step size, after many times of iteration, is used for rapid convergence. FIG. 11 shows a dummy program. α_(n) is an approach distance for each time of iteration, r_(n) is a residual error, a margin between a later solution x_(n) and a former solution x_(n−1) that are given after iteration, being used to determine whether the iteration stops; P_(n) is a conjugate direction, an approach direction for each time of iteration.

Finally, at step 6 shown in FIG. 3, a value may be obtained in the conjugate gradient algorithm. After the algorithm is compared with other methods, it is found that it is precise. It is nevertheless especially noted that it saves much more time to operate, the residual error as the condition stops the iteration depending on a user's setting so that the user may set up for required precision and operating rate. At the same time, determination is made whether it meets the user's request at step 7 shown in FIG. 3. If it does, a result is outputted at step 9 shown in FIG. 3; if it does not, fine tune is done for an ideal skew at step 8 shown in FIG. 3. Next, steps 5, 6, and 7 shown in FIG. 3 are repeated until it meets the required conditions.

Simple Embodiments of this Invention

As shown in FIG. 3 illustrating a flow chart of a program, after the Lagrange multiplier λ=2M⁻¹Bg is obtained in the conjugate gradient algorithm and then put in equation (17) for a feasible solution to the skew, before the program ends, determination is made whether all the skews meet Bs=0 and l≦s≦u, and if it does, correction and calculation must continue. Fine tune is done for the ideal skew g and then calculation is made again for the feasible solution to the skew. After it meets the condition, the obtained feasible solutions to all the skews are outputted.

Fine Tune for Ideal Skew

If the obtained skew does not meet any threshold condition, then the skew s is out of the safe range. At this time, fine tune must be made for the ideal skew g. If the obtained skew s is higher than the upper bound of safe range, the ideal clock g is lowered; contrarily, if the obtained skew s is lower than the lower bound of safe range, the ideal clock g is heightened. The volume of ideal clock g is adjusted depending on the margin between the skew s and the boundary value of safe range, indicating when that the skew s is much far from the boundary value of safe range, larger adjustment of the ideal clock g is made; contrarily, when that the skew s is less far from the boundary value of safe range, smaller adjustment of the ideal clock g is made. Adjustment is thus made by degree until the obtained skew s meets the threshold condition, and the iteration stops.

Implementation Result

Operation platforms used in this invention are SUN Blade 2000 as a workstation, Solaris 8 as an operating system, Ansi C for design, and a gcc compiler. ISCAS'89 is applied as a testing circuit. A smaller circuit is herein used to generate an output file as an example after the operation is performed in this invention, and the output file contains the total amounts of circuit logic gates, the number of registers, the number of local data paths, clock periods, and feasible solutions to all the skews.

Line 1 indicates a circuit name, r, p, Spanning, Clock, CG#, Residual, and Run Time in lines 2˜9 indicate the number of registers, the number of local data paths, the number of spanning tree nodes, clock period, number of times of iteration in the conjugate gradient algorithm,.residual error, number of times for calculation of the skew s, and running time of the program, respectively, and line 9 indicates running time of the program in the conventional technology, in which * stands for the minimum.

Experimental Analysis

Zero Skew is compared with Non-Zero Skew for the reliability of a circuit, two ISCAS'89 testing circuits, s838.1 and s5378, are determined to be examples, analysis results are shown in FIGS. 8A, 8B, 9A, and 9B, zero skews are shown in FIGS. 8A and 9A, and non-zero skews are shown in FIGS. 8B and 9B. In FIGS. 8A and 9A, it is apparent that when the skew is at 0, the distribution range is wide. Thus, being close to the boundary value of safe range, the zero skew might also be out of the boundary value of safe range, so it is not good to the reliability of circuit. On the contrary, in FIGS. 8B and 9B, the obtained feasible solutions to the skews in the safe range are obviously concentrated in the center, indicating that they are very close to the ideal skew; thus, the reliability and performance of circuit increase.

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures. 

1. A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization, comprising: step 1 of reading a test circuit, a circuit to be tested being first read in the program; step 2 of building up a circuit model, pre-processing of and correlation analysis on the circuit being made; step 3 of building up a minimum spanning tree; at step 4 of building up a matrix M=B×B^(t); step 5 of calculating a Lagrange multiplier, a Conjugate Gradients algorithm being used to calculate a Lagrange multiplier; step 6 of calculation for a feasible solution to a skew; and step 7 of outputting a result.
 2. The method of designing the synchronous circuit of VLSI for Clock Skew scheduling and optimization according to claim 1, wherein the minimum spanning tree must work with the Depth First Search algorithm to efficiently form all the loops in the circuit, and the loop set are a matrix B: $B = {\begin{bmatrix} 1 & 0 & 0 & 0 & {- 1} & 1 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & {- 1} & 1 & 1 \\ 0 & 0 & 1 & 0 & 0 & {- 1} & 1 & 1 \\ 0 & 0 & 0 & 1 & 0 & {- 1} & 1 & 0 \end{bmatrix} = \left\lbrack {I\mspace{14mu} C} \right\rbrack}$ and after the matrix B is constructed, the quadratic equation programming may be executed.
 3. The method of designing the synchronous circuit of VLSI for Clock Skew scheduling and optimization according to claim 1, wherein the iteration of the conjugate gradient algorithm is used to obtain the Lagrange multiplier λ=2M ⁻¹ B g, in which when a residual error as a condition is small enough to stop the iteration, a set of operation result is generated; in the mathematic issue of Ax=b, the residual error is the sum of errors between a former set of x and a later set of x Ax=b; enough small residual error indicates that the value x obtained in the conjugate gradient algorithm almost approaches a correct value x, and thus the iteration stops.
 4. The method of designing the synchronous circuit of VLSI for Clock Skew scheduling and optimization according to claim 1, wherein a circuit model is formed at step 2 of pre-processing of and correlation analysis on the circuit.
 5. The method of designing the synchronous circuit of VLSI for Clock Skew scheduling and optimization according to claim 1, wherein linear-related analysis on the circuit must be carried out at step 2 of pre-processing of and correlation analysis on the circuit.
 6. The method of designing the synchronous circuit of VLSI for Clock Skew scheduling and optimization according to claim 1, wherein steps 6-1 and 6-2 are included between steps 6 and 7, in which step 6-1 indicates the comparison of conditions for conformity with a condition Bs=0, l<s<u, and step 6-2 indicates that if no conformity with the condition at step 6-1 occurs, then fine tune is made for an ideal skew and step 5 returns, and if conformity with the condition at step 6-1 occurs, then step 7 is executed. 